1. Field of the Invention
The present invention relates to a design method, a design apparatus, a design program of a semiconductor device, and a semiconductor device, and more specifically, to a design method, a design apparatus, and a design program of a semiconductor device that suppress characteristic variations of semiconductor elements in manufacturing, and a semiconductor device designed by the design method, the design apparatus, and the design program.
2. Description of Related Art
In recent years, advancement of technique for achieving segmentation of manufacturing processes attains high performance in functions to be mounted in semiconductor devices. However, segmentation of the manufacturing processes makes it difficult to suppress structural variations of the semiconductor elements caused in manufacturing, which increases characteristic variations of semiconductor elements. Since the characteristic variations of semiconductor elements influence on the yield, suppression of characteristic variations is important to stably produce semiconductor devices.
One of the methods of suppressing characteristic variations of semiconductor elements in manufacturing is disclosed in Japanese Unexamined Patent Application Publication No. 2008-211214. In the technique disclosed in Japanese Unexamined Patent Application Publication No. 2008-211214, a dummy element is inserted into a layout pattern of the semiconductor device. Accordingly, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2008-211214 decreases the difference in pattern density for each area in the chip, and suppresses the variations in the device structure caused in the etching processing in the manufacturing process.
However, another factor that causes structural variations of semiconductor elements is heating variations in an annealing process that diffuses impurities in a diffusion region of semiconductor elements. The technique disclosed in Japanese Unexamined Patent Application Publication No. 2008-211214 cannot suppress characteristic variations of semiconductor elements in this annealing process.
In the annealing process, a semiconductor substrate is heated to diffuse impurities implanted into the semiconductor substrate. At this time, the diffusion state of impurities is varied according to the heating condition or the amount of impurities implanted therein. Moreover, in recent years, a technique called lamp annealing is employed in the annealing process in order to reduce the time required for manufacturing. In the lamp annealing, the semiconductor substrate is heated in an extremely short time (for example, a few seconds (spike lamp annealing), 0.1 msec to 100 msec (millisecond lamp annealing)). On the other hand, the semiconductor element is composed of a plurality of regions, and a first member (for example, diffusion region) and a second member (for example, device isolation region, gate electrode, and so on) forming a plurality of regions have different heat reflective properties. Thus, when the semiconductor device is manufactured by the lamp annealing process, there is caused variations in the heating state according to the ratio of the first member to the second member. When the semiconductor device is manufactured using the lamp annealing, an influence of heating variations due to the ratio of the members prominently appears. A method of suppressing the structural variations in the semiconductor elements in such annealing process is disclosed in Japanese Unexamined Patent Application Publication No. 2008-171170.
Japanese Unexamined Patent Application Publication No. 2008-171170 discloses a semiconductor wafer structure that includes a first device including epitaxially-grown silicon germanium of a first reflectance ratio and a second device including monocrystal silicon of a second reflectance ratio, in which a non-functional dummy first device including silicon germanium and a non-functional dummy second device including monocrystal silicon are distributed for the whole wafer so as to achieve the same overall ratio and the density as the distribution of the first and second devices. Accordingly, in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2008-171170, uniform temperature change for the whole wafer is attained in the lamp annealing process.